SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 145

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals and
Registers, on page 7-33 covers ESSI GPIO.
7.5.1 ESSI Control Register A (CRA)
The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct
the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word
length, and number of words per frame for serial data.
Freescale Semiconductor
Bit Number
PSR
23
11
23
22
—Reserved bit; read as 0; write to 0 for future compatibility.
SSC1
22
10
Bit Name
SSC1
WL2
21
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
9
Reset Value
Figure 7-2. ESSI Control Register A(CRA)
WL1
20
8
0
0
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
WL0
PM7
DSP56303 User’s Manual, Rev. 2
19
7
Reserved. Write to 0 for future compatibility.
Select SC1
Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal is configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is
configured as output (SCD1 = 1).
ALC
PM6
18
6
PM5
17
5
DC4
PM4
16
4
Description
DC3
PM3
15
3
DC2
PM2
ESSI Programming Model
14
2
PM1
DC1
13
1
PM0
DC0
12
0
7-13