SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 240

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bootstrap Program
M_XTLD
M_PSTP
M_PEN
M_PCOD
M_PD
;---------------------------------------------------------------
A.10 Bus Interface Unit (BIU) Equates
;---------------------------------------------------------------
;
M_BCR
M_DCR
M_AAR0
M_AAR1
M_AAR2
M_AAR3
M_IDR
;
M_BA0W
M_BA1W
M_BA2W
M_BA3W
M_BDFW
M_BBS
M_BLH
M_BRH
;
M_BCW
M_BRW
M_BPS
M_BPLE
M_BME
M_BRE
M_BSTR
M_BRF
M_BRP
;
M_BAT
M_BAAP
M_BPEN
A-18
Register Addresses Of BIU
Bus Control Register
DRAM Control Register
Address Attribute Registers
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$F00000
16
17
18
19
$FFFFFB
$FFFFFA
$FFFFF9
$FFFFF8
$FFFFF7
$FFFFF6
$FFFFF5 ;
$1F
$3E0
$1C00
$E000
$1F0000; Default Area Wait Control Mask (BDFW0-BDFW4)
21
22
23
$3
$C; Out Of Page Wait States Bits Mask (BRW0-BRW1)
$300
11
12
13
14
$7F8000
23
$3
2
3
;Mask BAT(1:0)
; External Access Type and Pin Definition Bits
; PreDivider Factor Bits Mask (PD0-PD3)
;ID Register
; XTAL Disable Bit
; STOP Processing State Bit
; PLL Enable Bit
; PLL Clock Output Disable Bit
; Bus Control Register
; DRAM Control Register
; Address Attribute Register 0
; Address Attribute Register 1
; Address Attribute Register 2
; Address Attribute Register 3
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
; Area 2 Wait Control Mask (BA2W0-BA2W2)
; Area 3 Wait Control Mask (BA3W0-BA3W3)
; Bus State
; Bus Lock Hold
; Bus Request Hold
; In Page Wait States Bits Mask (BCW0-BCW1)
; DRAM Page Size Bits Mask (BPS0-BPS1)
; Page Logic Enable
; Mastership Enable
; Refresh Enable
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
; Refresh prescaler
; Address Attribute Pin Polarity
; Program Space Enable
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor