SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 64

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
4.2 Bootstrap Program
The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap ROM
located in program memory space at locations $FF0000–$FF00BF. The bootstrap program can
load any program RAM segment from an external byte-wide EPROM, the SCI, or the host port.
The bootstrap program code is listed in Appendix 4, Core Configuration.
Upon exit from the Reset state, the DSP56303 samples the
their values into OMR[MA–MD]. The mode input signals (
MB, MC, and MD bits determine which bootstrap mode the DSP56303 enters (see Table 4-1).
Note:
You can invoke the bootstrap program options (except modes $0 and $8) at any time by writing
the appropriate values to the MA, MB, MC, and MD bits in the OMR and jumping to the
bootstrap program entry point, $FF0000. Software can set the mode selection bits directly in the
OMR. Bootstrap modes 0 and 8 are the normal DSP56303 functioning modes. The other
bootstrap modes select different specific bootstrap loading source devices. Refer to Appendix A,
Bootstrap Program for details on the bootstrap program.
In these modes, the bootstrap program expects the following data sequence when downloading
the user program through an external port:
Note:
When the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.3 Central Processor Unit (CPU) Registers
Two CPU registers must be configured to initialize operation. The Status Register (SR) selects
various arithmetic processing protocols and contains several status reporting flag bits. The
Operating Mode Register (OMR) configures several system operating modes and characteristics.
4-6
1.
2.
3.
Three bytes that specify the number of (24-bit) program words to load .
Three bytes that specify the (24-bit) start address where the user program loads in the
DSP56303 program memory.
The user program (three bytes for each 24-bit program word).
To stop the bootstrap in any HI08 bootstrap mode, set the Host Flag 0 (HF0). The
loaded user program begins executing from the specified starting address.
The three bytes for each data sequence are loaded LSB first.
DSP56303 User’s Manual, Rev. 2
MODA
MODA
–
–
MODD
MODD
) and the resulting MA,
signal lines and loads
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