SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 59

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
This chapter presents DSP56300 core configuration details specific to the DSP56303, including:
For information on specific registers or modules in the DSP56300 core, refer to the DSP56300
Family Manual.
4.1 Operating Modes
The DSP56303 begins operation by leaving the Reset state and going into one of eight operating
modes. As the DSP56303 exits the Reset state, it loads the values of
MODD
operating mode, which in turn determines the bootstrap program option the DSP uses to start up.
Software can also set the OMR[MA–MD] bits directly. A jump directly to the bootstrap program
entry point ($FF0000) after the OMR bits are set causes the DSP56303 to execute the specified
bootstrap program option (except modes $0 and $8). Table 4-1 shows the DSP56303 bootstrap
operation modes, the corresponding settings of the external operational mode signal lines (the
OMR[MA–MD] bits), and the reset vector address to which the DSP56303 jumps once it leaves
the Reset state.
Freescale Semiconductor
into bits MA, MB, MC, and MD of the OMR. These bit settings determine the DSP
Operating modes
Bootstrap program
Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
Interrupt Priority Registers (IPRC and IPRP)
PLL control (PCTL) register
Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
DMA Control Registers 5–0 (DCR[5–0])
Device identification register (IDR)
JTAG identification register
JTAG boundary scan register (BSR)
DSP56303 User’s Manual, Rev. 2
MODA
,
MODB
,
MODC
, and
4
4-1