SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 39

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Freescale Semiconductor
SC10
PD0
SC11
PD1
SC12
PD2
Signal
Name
Input or Output
Input/Output
Input or Output
Input/Output
Input or Output
Type
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1)
Input
Input
Input
Reset
State During
Disconnected
Disconnected
Disconnected
internally
internally
internally
Stop
DSP56303 User’s Manual, Rev. 2
1
Serial Control 0
Functions in either Synchronous or Asynchronous mode. For
Asynchronous mode, this signal is the receive clock I/O
(Schmitt-trigger input). For Synchronous mode, this signal is either
for Transmitter 1 output or Serial I/O Flag 0.
Port D 0
The default configuration following reset is GPIO. For PD0, signal
direction is controlled through the Port D Direction Register
(PRRD).
This signal is configured as SC10 or PD0 through the Port D
Control Register (PCRD). This input is 5 V tolerant.
Serial Control 1
Functions in either Synchronous or Asynchronous mode. For
Asynchronous mode, this signal is the receiver frame sync I/O. For
Synchronous mode, this signal is either Transmitter 2 output or
Serial I/O Flag 1.
Port D 1
The default configuration following reset is GPIO. For PD1, signal
direction is controlled through PRRD.
This signal is configured as SC11 or PD1 through PCRD. This
input is 5 V tolerant.
Serial Control Signal 2
The frame sync for both the transmitter and receiver in
Synchronous mode, and for the transmitter only in Asynchronous
mode. When configured as an output, this signal is the internally
generated frame sync signal. When configured as an input, this
signal receives an external frame sync signal for the transmitter
(and the receiver in synchronous operation).
Port D 2
The default configuration following reset is GPIO. For PD2, signal
direction is controlled through PRRD.
This signal is configured as SC12 or PD2 through PCRD. This
input is 5 V tolerant.
Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal Description
2-15