SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 261

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
DMA Control Registers (DCR5–DCR0)
Reset = $000000
DMA Channel Enable, Bit 23
0 = Disables channel operation
1 = Enables channel operation
Application:
DMA Interrupt Enable, Bit 22
0 = Disables DMA Interrupt
1 = Enables DMA interrupt
23 22 21 20
DE
DMA Transfer Mode, Bits 21–19
DTM[2:0]
DIE
DMA Channel Priority, Bits 18–17
DMA Continuous Mode Enable, Bit 16
0 = Disables continuous mode
1 = Enables continuous mode
000
001
010
011
100
101
110
111
DPR[1:0]
00
01
10
11
DMA Request Source, Bits 15–11
10101 - 11111
DTM[2–0]
00000–00011
00100–01001
01010–01011
01100–01101
01110–01111
10000–10010
request
request
request
DE
request
request
reserved
reserved
DRS[4:0]
Triggered By
10011
10100
Priority level 0 (lowest)
Priority level 1
Priority level 2
Priority level 3 (highest)
19 18 17 16
Figure B-8. DMA Control Registers 5–0 (DCR[5–0])
DPR[1–0] DCON
External (IRQA, IRQB, IRQC, IRQD)
Transfer done from channel 0,1,2,3,4,5
ESSI0 Receive, Transmit Data
ESSI1 Receive, Transmit Data
SCI Receive, Transmit Data
Timer0, Timer1, Timer2
Host Receive Data Full
Host Transmit Data Empty
Reserved
Channel Priority
yes
yes
yes
yes
no
no
DE Cleared
Requesting Device
15 14 13 12 11 10 9
DSP56303 User’s Manual, Rev. 2
block transfer
word transfer
line transfer
block transfer
block transfer
word transfer
Transfer Mode
DRS[4–0]
X:$FFFFD8, X:$FFFFDC, X:$FFFFE0,
X:$FFFFE4, X:$FFFFE8, X:$FFFFEC
1 = Three-Dimensional mode enabled
Three-Dimensional Mode, Bit 10
0 = Three-Dimensional mode disabled
D3D
Three-Dimensional Addressing Modes (D3D=1)
DMA Address Mode, Bits 9–4
Non-Three-Dimensional Addressing Modes (D3D=0)
DAM[2–0] = source
DAM[5:3]
DAM[2:0]
DAM[5:3]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
8
DMA Destination Space, Bits 3–2
2D
2D
2D
2D
No update
Postincrement-by-1
reserved
reserved
DMA Source Space, Bits 1–0
Addressing Mode
DSS[1:0]
2D
2D
2D
2D
No update
Postincrement-by-1
3D
3D
DAM[5–0]
7
DSS[1:0]
00
01
10
11
Addressing Mode
00
01
10
11
6
Date:
Programmer:
X Memory Space
Y Memory Space
P Memory Space
Reserved
5
DAM[5–3] = Destination
X Memory Space
Y Memory Space
P Memory Space
Reserved
DMA Destination Memory
B
B
B
B
A
A
4
Counter
Mode
DMA Source Memory
DOR0
DOR1
DOR2
DOR3
None
None
DOR0: DOR1
DOR2: DOR3
DDS[1–0]
3
Read/Write
Offset Selection
Programming Sheets
DMA
DOR0
DOR1
DOR2
DOR3
None
None
2
Offset Register
Selection
Sheet 1 of 1
DSS[1–0]
1
0
B-17