SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 146

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
7-14
Bit Number
21–19
18
17
Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Name
WL[2–0]
ALC
Reset Value
0
0
DSP56303 User’s Manual, Rev. 2
Word Length Control
Select the length of the data words transferred via the ESSI. Word lengths of
8-, 12-, 16-, 24-, or 32-bits can be selected. The ESSI data path programming
model in Figure 7-12 and Figure 7-13 shows additional information on how to
select different lengths for data words. The ESSI data registers are 24 bits
long. The ESSI transmits 32-bit words in one of two ways:
• By duplicating the last bit 8 times when WL[2–0] = 100
• By duplicating the first bit 8 times when WL[2–0] = 101.
Note:
Note:
Alignment Control
The ESSI handles 24-bit fractional data. Shorter data words are left-aligned to
the MSB, bit 23. For applications that use 16-bit fractional data, shorter data
words are left-aligned to bit 15. The ALC bit supports shorter data words. If
ALC is set, received words are left-aligned to bit 15 in the receive shift register.
Transmitted words must be left-aligned to bit 15 in the transmit shift register. If
the ALC bit is cleared, received words are left-aligned to bit 23 in the receive
shift register. Transmitted words must be left-aligned to bit 23 in the transmit
shift register.
Note:
Reserved. Write to 0 for future compatibility.
WL2
0
0
0
0
1
1
1
1
When WL[2–0] = 100, the ESSI is designed to duplicate the last bit of
the 24-bit transmission eight times to fill the 32-bit shifter. Instead,
after the 24-bit word is shifted correctly, eight zeros (0s) are shifted.
When the ESSI transmits data in On-Demand mode (that is, MOD = 1
in the CRB and DC[4–0]=00000 in the CRA) with WL[2–0] = 100, the
transmission does not work properly. To ensure correct operation, do
not use On-Demand mode with the WL[2–0] = 100 32-bit word length
mode.
If the ALC bit is set, only 8-, 12-, or 16-bit words are used. The use of
24- or 32-bit words leads to unpredictable results.
WL1
0
0
1
1
0
0
1
1
ESSI Word Length Selection
Description
WL0
0
1
0
1
0
1
0
1
(valid data in the first 24
(valid data in the last 24
Number of Bits/Word
Freescale Semiconductor
Reserved
Reserved
bits)
bits)
12
16
24
32
32
8