SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 74

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
The DSP56303 has a four-level interrupt priority structure. Each interrupt has two interrupt
priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest
priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL bits.
The IPRC also selects the trigger mode of the external interrupts (
IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is
negative-edge-triggered.
4.4.2 Interrupt Table Memory Map
Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries for
interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The
DSP56303 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are used
for specific interrupt sources. The remaining interrupt vectors are reserved and can be used for
host
be used for program or data storage.
4-16
xxL1
0
0
1
1
NMI
IPL bits
(IPL = 3) or for host command interrupt (IPL = 2). Unused interrupt vector locations can
23
11
Reserved bit; read as zero; should be written with zero for future compatibility
Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)
xxL0
0
1
0
1
22
10
T0L1
21
9
T0L0
Interrupts Enabled
20
8
Table 4-4. Interrupt Priority Level Bits
SCL1
Yes
Yes
Yes
No
19
7
DSP56303 User’s Manual, Rev. 2
SCL0
18
6
S1L1
17
5
S1L0
16
4
Interrupts Masked
S0L1
15
3
0, 1, 2
0, 1
—
S0L0
0
14
2
HPL1
13
1
IRQA
HPL0
12
0
–
IRQD
Interrupt Priority Level
reserved
reserved
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IPL
TRIPLE TIMER IPL
). If the value of the
Freescale Semiconductor
0
1
2
3