SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 91

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.8 Device Identification Register (IDR)
The IDR is a read-only factory-programmed register that identifies DSP56300 family members.
It specifies the derivative number and revision number of the device. This information is used in
testing or by software. Figure 4-10 shows the contents of the IDR. Revision numbers are
assigned as follows: $0 is revision 0, $1 is revision A, and so on.
.
Freescale Semiconductor
Number
9–4
3–2
1–0
Bit
Bit Name
DDS[1–0]
DAM
DSS
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
23
Figure 4-10. Identification Register Configuration (Revision E)
Reserved
Reset
Value
$00
0
0
0
DMA Address Mode
Defines the address generation mode for the DMA transfer. These bits are encoded in two
different ways according to the D3D bit.
DMA Destination Space
Specify the memory space referenced as a destination by the DMA.
Note:
DMA Source Space
Specify the memory space referenced as a source by the DMA.
Note:
16
15
DDS1
DSS1
In Cache mode, a DMA to Program memory space has some limitations (as
described in Chapter 3, Memory Configuration.
In Cache mode, a DMA to Program memory space has some limitations (as
described in Chapter 3, Memory Configuration.
Revision Number
0
0
1
1
0
0
1
1
DSP56303 User’s Manual, Rev. 2
$5
12
DDS0
DSS0
0
1
0
1
0
1
0
1
11
Description
Derivative Number
X Memory Space
Y Memory Space
P Memory Space
Reserved
X Memory Space
Y Memory Space
P Memory Space
Reserved
DMA Destination Memory Space
$303
DMA Source Memory Space
Device Identification Register (IDR)
0
4-33