SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 106

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Interface (HI08)
The choice of which protocol to use is based on such system constraints as the amount of data to
be transferred, the timing requirements for the transfer, and the availability of such resources as
processing bandwidth and DMA channels. All of these constraints are discussed in the following
sections. The transfers described here occur asynchronously between the host and the DSP; each
transferring data at its own pace. However, use of the appropriate handshaking protocol allows
data transfers to occur at optimum rates.
6.4.1 Software Polling
Software polling is the simplest data transfer method to use, but it demands the greatest amount
of the core’s processing power. Status bits are provided for the host or the DSP core to test and
determine if the data registers are empty or full. However, the DSP core cannot be involved in
other processing activities while it is polling these status bits.
On the DSP side, for transfers from the DSP to the host (host reads), the DSP core must
determine the state of Host Transmit Data register (HTX). In transfers from the host to the DSP
(host writes), the DSP side should determine the state of the Host Receive Data Register (HRX).
Thus, two bits are provided to the core for polling:
A similar mechanism is available on the host-side to determine the state of the Transmit Registers
(TXH:TXM:TXL) and Receive Registers (RXH:RHM:RHL). Two bits are provided to the host
for polling:
The HI08 also offers four general-purpose flags for communication between the host and the
DSP. The DSP-side uses the HSR Host Flag bits (HCR[4–3] = HF[3–2]) to pass
application-specific information to the host. The status of HF3–HF2 is reflected in the host-side
ISR Host Flag bits (ISR[4–3] = HF[3–2]). Similarly, the host side can use the ICR Host Flag bits
(ICR[4–3] = HF[1–0]) to pass application-specific information to the DSP. The status of HF[1–0]
is reflected in the DSP-side HSR Host Flag bits (HSR[4–3] = HF[1–0]).
6.4.2 Core Interrupts and Host Commands
The HI08 can request interrupt service from the DSP56303 core. The DSP56303 core interrupts
are internal and do not require the use of an external interrupt signal. When the appropriate
interrupt enable bit in the HCR is set, an interrupt condition caused by the host interface sets the
appropriate bit in the HSR, generating an interrupt request to the DSP56303 interrupt controller
(see Figure 6-2). The DSP56303 acknowledges interrupts by jumping to the appropriate interrupt
service routine. The following DSP core interrupts are possible from the HI08 peripheral:
6-6
the Host Transmit Data Empty (HTDE) bit in the Host Status register (HSR[1]:HTDE)
the Host Receive Data Full (HRDF) bit in the Host Status register (HSR[0]:HRDF)
the Transmit Data Empty (TXDE) bit in the Interface Status Register (ISR[1]:TXDE)
the Receive Data Full (RXDF) bit in the Interface Status Register (ISR[0]:RXDF)
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor