SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 239

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M_DAM0 EQU4
M_DAM1 EQU5
M_DAM2 EQU6
M_DAM3 EQU7
M_DAM4 EQU8
M_DAM5 EQU9
M_D3D
M_DRS
M_DCON EQU16
M_DPR
M_DPR0 EQU17
M_DPR1 EQU18
M_DTM
M_DTM0 EQU19
M_DTM1 EQU20
M_DTM2 EQU21
M_DIE
M_DE
;
M_DTD
M_DTD0
M_DTD1
M_DTD2
M_DTD3
M_DTD4
M_DTD5
M_DACT EQU 8
M_DCH
M_DCH0 EQU 9
M_DCH1 EQU 10
M_DCH2 EQU 11
;---------------------------------------------------------------
A.9 Phase Locked Loop (PLL) equates
;---------------------------------------------------------------
;
M_PCTL
;
M_MF
M_DF
M_XTLR
Freescale Semiconductor
EQU 10
EQU$F800
EQU$60000
EQU$380000
EQU22
EQU23
EQU $3F
EQU $E00
DMA Status Register
EQU
EQU
EQU
EQU
EQU
EQU
Register Addresses Of PLL
PLL Control Register
EQU
EQU
EQU
EQU
$FFFFFD
$FFF
$7000
15
0
1
2
3
4
5
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
; DMA Address Mode 5
; DMA Three Dimensional Mode
; DMA Request Source Mask (DRS0-DRS4)
; DMA Continuous Mode
; DMA Channel Priority
; DMA Channel Priority Level (low)
; DMA Channel Priority Level (high)
; DMA Transfer Mode Mask
;(DTM2-DTM0)
; DMA Transfer Mode 0
; DMA Transfer Mode 1
; DMA Transfer Mode 2
; DMA Interrupt Enable bit
; DMA Channel Enable bit
;Channel Transfer Done Status MASK
; DMA Active State
; DMA Active Channel Mask
: (DCH0DCH2)
; DMA Active Channel 0
; DMA Active Channel 1
; DMA Active Channel 2
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; PLL Control Register
; Multiplication Factor Bits Mask (MF0-MF11)
; Division Factor Bits Mask (DF0-DF2)
; XTAL Range select bit
DSP56303 User’s Manual, Rev. 2
Phase Locked Loop (PLL) equates
A-17