SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 21

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
1.8 DMA
The DMA block has the following features:
Freescale Semiconductor
EXTAL
PINIT/NMI
XTAL
Six DMA channels supporting internal and external accesses
One-, two-, and three-dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
RESET
See Section 1.6.6, Internal Memory, on page 1-9 for memory size details.
2
Bootstrap
Internal
Timer
Switch
Generator
Triple
Six-Channel
ROM
Data
Generation
DMA Unit
Bus
Clock
Address
PLL
Unit
Interface
16
Host
HI08
Controller
Program
Interrupt
Figure 1-1. DSP56303 Block Diagram
6
Interface
Expansion Area
ESSI
6
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Peripheral
DSP56303 User’s Manual, Rev. 2
Controller
Program
Decode
Interface
3
SCI
Generator
Program
Address
Program RAM
4096 × 24 bits
(default)
DSP56300
24-Bit
Core
DDB
YDB
XDB
PDB
GDB
24
DAB
YAB
XAB
PAB
Two 56-bit Accumulators
×
56-bit Barrel Shifter
24 + 56
2048 × 24
(default)
X Data
RAM
bits
Data ALU
→
56-bit MAC
2048
(default)
Y Data
RAM
bits
×
24
Expansion
Interface
Data Bus
I-Cache
Management
External
Address
External
Control
External
Switch
Switch
Memory
Bus
Bus
and
Power
Area
OnCE
JTAG
Address
Control
Data
DE
18
13
24
5
DMA
1-11