SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 108

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Interface (HI08)
Note:
6.4.3 Core DMA Access
The DSP56300 family Direct Memory Access (DMA) controller permits transfers between
internal or external memory and I/O without any core intervention. A DMA channel can be set up
to transfer data to/from the HTX and HRX data registers, freeing the core to use its processing
power on functions other than polling or interrupt routines for the HI08. DMA may well be the
best method to use for data transfers, but it requires that one of the six DMA channels be
available for use. Two HI08 DMA sources are possible, as Table 6-4 shows. Refer to the
DSP56300 Family Manual to learn about DMA accesses.
Note:
6.4.4 Host Requests
A set of signal lines allow the HI08 to request service from the host. The request signal lines
normally connect to the host interrupt request pins (IRQx) and indicate to the host when the DSP
HI08 port requires service. The HI08 can be configured to use either a single Host Request
(HREQ) line for both receive and transmit requests or two signal lines, a Host Transmit Request
(HTRQ) and a Host Receive Request (HRRQ), for each type of transfer.
Host requests are enabled on both the DSP-side and host-side. On the DSP side, the HPCR Host
Request Enable bit (HPCR[4] = HREN) is set to enable host requests. On the host side, clearing
the ICR Double Host Request bit (ICR[2] = HDRQ) configures the HI08 to use a single request
line (HREQ). Setting the ICR[2] = HDRQ bit enables both transmit and request lines to be used.
Further, the host uses the ICR Receive Request Enable bit (ICR[0] = RREQ) and the ICR
Transmit Request Enable bit (ICR[1] = TREQ) to enable receive and transmit requests,
6-8
Host Transmit Data Empty (HTDE = 1)
Host Receive Data Full (HRDF = 1)
When the DSP enters Stop mode, the HI08 pins are electrically disconnected
internally, thus disabling the HI08 until the core leaves Stop mode. Do not issue a
STOP command via the HI08 unless some other mechanism for exiting this mode is
provided.
available in the host-side data registers using an appropriate polling mechanism.
DMA transfers do not access the host bus. The host must determine when data is
Requesting Device
Table 6-4. DMA Request Sources
DSP56303 User’s Manual, Rev. 2
DCRx[15–11] = DRS[4–0]
10011
10100
Freescale Semiconductor