SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 134

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
Additional synchronization signals delineate the word frames. The Normal mode of operation
transfers data at a periodic rate, one word per period. The Network mode is similar in that it is
also for periodic transfers; however, it supports up to 32 words (time slots) per period. The
Network mode can be used to build time division multiplexed (TDM) networks. In contrast, the
On-Demand mode is for nonperiodic transfers of data. This mode, which offers a subset of the
Freescale Serial Peripheral Interface (SPI) protocol, can transfer data serially at high speed when
the data become available. Since each ESSI unit can be configured with one receiver and three
transmitters, the two units can be used together for surround sound applications (which need two
digital input channels and six digital output channels).
7.1 ESSI Enhancements
The DSP56000 SSI is enhanced in the following ways to make the ESSI:
7.2 ESSI Data and Control Signals
Three to six signals are required for ESSI operation, depending on the operating mode selected.
The serial transmit data (
synchronized to the clock if they are programmed as transmit-data signals.
7.2.1 Serial Transmit Data Signal (STD)
The
transmitted from the TX0 shift register. With an internally-generated bit clock, the
becomes a high impedance output signal for a full clock period after the last data bit is
transmitted if another data word does not follow immediately. If sequential data words are
7-2
STD
Network enhancements
— Time slot mask registers (receive and transmit)
— End-of-frame interrupt
— Drive enable signal (used with transmitter 0)
Audio enhancements
— Three transmitters per ESSI (for six-channel surround-sound)
General enhancements
— Can trigger DMA interrupts (receive or transmit)
— Separate exception enable bits
Other changes
— One divide-by-2 step is removed from the internal clock source chain
— The CRA[PSR] bit definition is reversed
— Gated-Clock mode is not available
signal transmits data from the serial transmit shift register.
STD
) signal and serial control (
DSP56303 User’s Manual, Rev. 2
SC0
and
SC1
STD
) signals are fully
is an output when data is
Freescale Semiconductor
STD
signal