SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 202

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Triple Timer Module
9.3.1.4 Timer Event Counter (Mode 3)
In Mode 3, the timer counts external events and issues an interrupt (if interrupt enable bits are set)
when the timer counts a preset number of events. The timer clock signal can be taken from either
the TIO input signal or the prescaler clock output. If an external clock is used, it must be
internally synchronized to the internal clock, and its frequency must be less than the DSP56303
internal operating frequency divided by 4. The value of the TCSR[INV] bit determines whether
low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions increment the counter. If the
INV bit is set, high-to-low transitions increment the counter. If the INV bit is cleared,
low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, TCSR[TCF] is set and a compare
interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is
loaded with the value of the TLR when the next timer clock is received, and the count is resumed.
If the TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock. This
process repeats until the timer is disabled.
9-10
TC3
0
Mode 3 (internal clock): TRM = 1
N = write preload
M = write compare
TE
Clock
(TIO pin or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions.
TC2
Bit Settings
0
TC1
1
TC0
N
M
Figure 9-9. Event Counter Mode, TRM = 1
1
0
Mode
first event
DSP56303 User’s Manual, Rev. 2
3
N
Event Counter
Name
N + 1
Mode Characteristics
M
Function
Timer
N
if clock source
is from TIO pin,
TIO < CPUCLK + 4
interrupts every
M - N clock
periods
Freescale Semiconductor
Input
TIO
N + 1
External
Clock