SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 112

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Host Interface (HI08)
addressing modes. In addition, the MOVEP instruction allows direct data transfers between
DSP56303 internal memory and the HI08 registers or vice versa.
There are two types of host processor registers, data and control, with eight registers in all. The
DSP core can access all eight registers, but the external host cannot. The following data registers
are 24-bit registers used for high-speed data transfers by the DSP core.
The DSP-side control registers are 16-bit registers that control HI08 functionality:
Both hardware and software resets disable the HI08. After a reset, the HI08 signals are
configured as GPIO and disconnected from the DSP56300 core (that is, the signals are left
floating).
6.6.1 Host Control Register (HCR)
This read/write register controls the HI08 interrupt operation. Initialization values for HCR bits
are presented in Section 6.6.9, DSP-Side Registers After Reset, on page 6-20.
6-12
Bit Number
15–5
4–3
Host data receive register (HRX), on page 6-19
Host data transmit register (HTX), on page 6-19
Host control register (HCR), on page 6-12
Host status register (HSR), on page 6-13
Host GPIO data direction register (HDDR), on page 6-14
Host GPIO data register (HDR), on page 6-15
Host base address register (HBAR), on page 6-15
Host port control register (HPCR), on page 6-16
15
—Reserved bit; read as 0; write to 0 for future compatibility.
14
Bit Name
HF[3 –2]
13
Figure 6-6. Host Control Register (HCR) (X:$FFFFC2)
Table 6-8. Host Control Register (HCR) Bit Definitions
12
Reset Value
11
0
0
10
DSP56303 User’s Manual, Rev. 2
Reserved. Write to 0 for future compatibility.
Host Flags 2, 3
General-purpose flags for DSP-to-host communication. The DSP core can
set or clear HF[3–2]. The values of HF[3–2] are reflected in the interface
status register (ISR); that is, if they are modified by the DSP software, the
host processor can read the modified values by reading the ISR. These two
general-purpose flags can be used individually or as encoded pairs in a
simple DSP-to-host communication protocol, implemented in both the DSP
and the host processor software. The bit value is indeterminate after an
individual reset.
9
8
7
6
5
Description
HF3
4
HF2
3
HCIE HTIE HRIE
Freescale Semiconductor
2
1
0