SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 260

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming Reference
B-16
Application:
Address Attribute Registers 3 (AAR3)
Address Attribute Registers 2 (AAR2)
Address Attribute Registers 1 (AAR1)
Address Attribute Registers 0 (AAR0)
BAC11
Reset = $000000
23 22 21 20
Bus Address to Compare, Bits 23–12
Bus Interface Unit
BAC[11–0] = address to compare to the
external address in order to decide
whether to assert the AA pin
BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BPAC
Bus Number of Address Bits to Compare, Bits 11–8
BNC[3–0] = number of bits (from BAC bits) that are
compared to the external address
(Combinations BNC[3–0] = 1111, 1110, 1101 are
reserved.)
19 18 17 16
Figure B-7. Address Attribute Registers (AAR[3–0])
15 14 13 12 11 10 9
DSP56303 User’s Manual, Rev. 2
X:$FFFFF6 Read/Write
X:$FFFFF7 Read/Write
X:$FFFFF8 Read/Write
X:$FFFFF9 Read/Write
Bus Packing Enable, Bit 7
0 = Disable internal packing/unpacking logic
1 = Enable internal packing/unpacking logic
Bus Access Type, Bits 1–0
8
BAT[1–0]
Bus Y Data Memory Enable, Bit 5
Bus X Data Memory Enable, Bit 4
Bus Program Memory Enable, Bit 3
0 = Disable AA pin and logic during
1 = Enable AA pin and logic during
0 = Disable AA pin and logic during
1 = Enable AA pin and logic during
0 = Disable AA pin and logic during
1 = Enable AA pin and logic during
Bus Address Attribute Polarity, Bit 2
0 =
1 =
7
00
01
10
11
external Y data space accesses
external Y data space accesses
external X data space accesses
external X data space accesses
external program space accesses
external program space accesses
AA/RAS
AA/RAS
*
Date:
Programmer:
0
6
*
BYEN BXEN BPEN BAAP BAT1 BAT0
Reserved
SRAM access
DRAM access
Reserved
5
= Reserved, Program as 0
signal is active low
signal is active high
4
Encoding
3
Freescale Semiconductor
Sheet 3 of 3
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1
0