SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 90

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
4-32
Number
15–11
Bit
10
Bit Name
DRS
D3D
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Reset
Value
0
0
DMA Request Source
Encodes the source of DMA requests that trigger the DMA transfers. The DMA request
sources may be external devices requesting service through the IRQA, IRQB, IRQC and
IRQD pins, triggering by transfers done from a DMA channel, or transfers from the internal
peripherals. All the request sources behave as edge-triggered synchronous inputs.
Peripheral requests 18–21 (DRS[4–0] = 111xx) can serve as fast request sources. Unlike a
regular peripheral request in which the peripheral can not generate a second request until
the first one is served, a fast peripheral has a full duplex handshake to the DMA, enabling a
maximum throughput of a trigger every two clock cycles. This mode is functional only in the
Word Transfer mode (that is, DTM = 001 or 101). In the Fast Request mode, the DMA sets
an enable line to the peripheral. If required, the peripheral can send the DMA a one cycle
triggering pulse. This pulse resets the enable line. If the DMA decides by the priority
algorithm that this trigger will be served in the next cycle, the enable line is set again, even
before the corresponding register in the peripheral is accessed.
Three-Dimensional Mode
Indicates whether a DMA channel is currently using three-dimensional (D3D = 1) or
non-three-dimensional (D3D = 0) addressing modes. The addressing modes are specified
by the DAM bits.
10101–11111
DSP56303 User’s Manual, Rev. 2
DRS[4–0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
Description
Host transmit data empty (HTDE = 1)
Host receive data full (HRDF = 1)
ESSI0 transmit data (TDE0 = 1)
ESSI1 transmit data (TDE1 = 1)
ESSI0 receive data (RDF0 = 1)
ESSI1 receive data (RDF1 = 1)
Transfer done from channel 0
Transfer done from channel 1
Transfer done from channel 2
Transfer done from channel 3
Transfer done from channel 4
Transfer done from channel 5
SCI transmit data (TDRE = 1)
SCI receive data (RDRF = 1)
Requesting Device
External (IRQA pin)
External (IRQB pin)
External (IRQC pin)
External (IRQD pin)
Timer0 (TCF0 = 1)
Timer1 (TCF1 = 1)
Timer2 (TCF2 = 1)
Reserved
Freescale Semiconductor