SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 40

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
2.10 Serial Communication Interface (SCI)
The Serial Communication interface (SCI) provides a full duplex port for serial communication
with other DSPs, microprocessors, or peripherals such as modems.
2-16
SCK1
PD3
SRD1
PD4
STD1
PD5
Notes: 1.
Signal
Name
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
Input/Output
Input or Output
Input
Input or Output
Output
Input or Output
The Wait processing state does not affect the signal state.
Type
Input
Input
Input
Reset
State During
Disconnected
Disconnected
Disconnected
internally
internally
internally
Stop
DSP56303 User’s Manual, Rev. 2
1
Serial Clock
Provides the serial bit rate clock for the ESSI interface for both the
transmitter and receiver in Synchronous modes, or the transmitter
only in Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside each
half of the serial clock.
Port D 3
The default configuration following reset is GPIO. For PD3, signal
direction is controlled through PRRD.
This signal is configured as SCK1 or PD3 through PCRD. This
input is 5 V tolerant.
Serial Receive Data
Receives serial data and transfers the data to the ESSI receive
shift register. SRD0 is an input when data is being received.
Port D 4
The default configuration following reset is GPIO. For PD4, signal
direction is controlled through PRRD. This signal is configured as
SRD1 or PD4 through PCRD. This input is 5 V tolerant.
Serial Transmit Data
Transmits data from the serial transmit shift register. STD1 is an
output when data is being transmitted.
Port C 5
The default configuration following reset is GPIO. For PD5, signal
direction is controlled through PRRD. This signal is configured as
STD1 or PD5 through PCRD. This input is 5 V tolerant.
Signal Description
Freescale Semiconductor