SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 199

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.1.2 Timer Pulse (Mode 1)
In Mode 1, the timer generates an external pulse on its TIO signal when the timer count reaches a
pre-set value. The TIO signal is loaded with the value of the TCSR[INV] bit. When the counter
matches the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The polarity of the TIO signal is inverted for one timer clock period. If
TCSR[TRM] is set, the counter is loaded with the TLR value on the next timer clock and the
count is resumed. If TCSR[TRM] is cleared, the counter continues to increment on each timer
clock. This process repeats until TCSR[TE] is cleared (disabling the timer).
The TLR value in the TCPR sets the delay between starting the timer and generating the output
pulse. To generate successive output pulses with a delay of X clock cycles between signals, set
the TLR value to X/2 and set the TCSR[TRM] bit. This process repeats until the timer is
disabled.
Freescale Semiconductor
TC3
0
Mode 1 (internal clock): TRM = 1
N = write preload
M = write compare
TC2
Bit Settings
0
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter (TCR)
TCPR
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
TC1
0
TC0
1
N
M
Figure 9-5. Pulse Mode (TRM = 1)
0
Mode
DSP56303 User’s Manual, Rev. 2
1
first event
N
Timer Pulse
Name
N + 1
Mode Characteristics
M
Function
Timer
N
pulse width =
timer clock
period
Output
TIO
N + 1
Operating Modes
Internal
Clock
9-7