SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 149

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.2 ESSI Control Register B (CRB)
CRB is one of two read/write control registers that direct the operation of the ESSI (see Figure
7-5). The CRB bit definitions are presented in Table 7-4. CRB controls the ESSI multifunction
signals, SC[2–0], which can be used as clock inputs or outputs, frame synchronization signals,
transmit data signals, or serial I/O flag signals.
The CRB contains the serial output flag control bits and the direction control bits for the serial
control signals. Also in the CRB are interrupt enable bits for the receiver and the transmitter. Bit
settings of the CRB determines how many transmitters are enabled: 0, 1, 2, or 3. The CRB
settings also determine the ESSI operating mode. Either a hardware
RESET instruction clears all the bits in the CRB. Table 7-2, Mode and Signal Definitions, on
page 7-4 summarizes the relationship between the ESSI signals
The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence follows for setting
output flags when transmitting data (by transmitter 0 through the
Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when the TX
data is transferred to the transmit shift register. The flag bit values are synchronized with the data
transfer. The timing of the optional serial output signals
and is not affected by the settings of TE2, TE1, TE0, or the receive enable (RE) bit of the CRB.
The ESSI has three transmit enable bits (TE[2–0]), one for each data transmitter. The process of
transmitting data from TX1 and TX2 is the same. TX0 differs from these two bits in that it can
also operate in Asynchronous mode. The normal transmit enable sequence is to write data to one
or more transmit data registers (or the Time Slot Register (TSR)) before you set the TE bit. The
normal transmit disable sequence is to set the Transmit Data Empty (TDE) bit and then to clear
the TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt Enable (TEIE) bits. In
Network mode, if you clear the appropriate TE bit and set it again, then you disable the
corresponding transmitter (0, 1, or 2) after transmission of the current data word. The transmitter
remains disabled until the beginning of the next frame. During that time period, the
Freescale Semiconductor
REIE
CKP
23
11
1.
2.
3.
Wait for TDE (TX0 empty) to be set.
Write the flags.
Write the transmit data to the TX register
TEIE
FSP
22
10
RLIE
FSR
21
9
Figure 7-5. ESSI Control Register B (CRB)
FSL1
TLIE
20
8
(ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)
FSL0
RIE
DSP56303 User’s Manual, Rev. 2
19
7
SHFD
TIE
18
6
SCKD
RE
17
5
SC[2–0]
SCD2
TE0
16
4
is controlled by the frame timing
SC[2–0]
STD
SCD1
TE1
15
3
RESET
signal only).
,
SCK
SCD0
TE2
signal or a software
14
ESSI Programming Model
, and the CRB bits.
2
MOD
OF1
13
1
SYN
OF0
12
0
7-17