SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 183

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.6.2 SCI Status Register (SSR)
The SSR is a read-only register that indicates the status of the SCI.
Freescale Semiconductor
Number
23–8
Bit
7
6
5
R8
23
15
7
Name
—Reserved bit; read as 0; write to 0 for future compatibility.
Bit
PE
R8
FE
FE
22
14
6
Reset
Value
Table 8-4. SCI Status Register (SSR) Bit Definitions
0
0
0
0
Reserved. Write to 0 for future compatibility.
Received Bit 8
In 11-bit Asynchronous Multidrop mode, the R8 bit indicates whether the received byte
is an address or data. R8 is set for addresses and is cleared for data. R8 is not affected
by reads of the SRX or SCI status register. A hardware RESET signal, a software
RESET instruction, an SCI individual reset, or a STOP instruction clears R8.
Framing Error Flag
In Asynchronous mode, FE is set when no stop bit is detected in the data string
received. FE and RDRE are set simultaneously when the received word is transferred to
the SRX. However, the FE flag inhibits further transfer of data into the SRX until it is
cleared. FE is cleared when the SCI status register is read followed by a read of the
SRX. A hardware RESET signal, a software RESET instruction, an SCI individual reset,
or a STOP instruction clears FE. In 8-bit Synchronous mode, FE is always cleared. If the
byte received causes both framing and overrun errors, the SCI receiver recognizes only
the overrun error.
Parity Error
In 11-bit Asynchronous modes, PE is set when an incorrect parity bit is detected in the
received character. PE and RDRF are set simultaneously when the received word is
transferred to the SRX. If PE is set, further data transfer into the SRX is not inhibited. PE
is cleared when the SCI status register is read, followed by a read of SRX. A hardware
RESET signal, a software RESET instruction, an SCI individual reset, or a STOP
instruction also clears PE. In 10-bit Asynchronous mode, 11-bit multidrop mode, and
8-bit Synchronous mode, the PE bit is always cleared since there is no parity bit in these
modes. If the byte received causes both parity and overrun errors, the SCI receiver
recognizes only the overrun error.
PE
21
13
5
Table 8-3. SCI Status Register
DSP56303 User’s Manual, Rev. 2
OR
20
12
4
IDLE
19
11
3
Description
RDRF
18
10
2
TDRE
SCI Programming Model
17
9
1
TRNE
16
8
0
8-15