SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 42

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signals/Connections
2.12 JTAG/OnCE Interface
2-18
TIO1
TIO2
Notes: 1.
TCK
TDI
TDO
TMS
TRST
Signal
Signal Name
Name
Input or
Output
Input or
Output
The Wait processing state does not affect the signal state.
Type
Input
Input
Output
Input
Input
Type
Input
Input
Reset
Table 2-15. Triple Timer Signals (Continued)
State During
Input
Input
Tri-stated
Input
Input
State During
Table 2-16. JTAG/OnCE Interface
Disconnected
Disconnected
internally
internally
Reset
Stop
DSP56303 User’s Manual, Rev. 2
1
Test Clock
A test clock signal for synchronizing JTAG test logic. This input is 5
V tolerant.
Test Data Input
A test data serial signal for test instructions and data. TDI is
sampled on the rising edge of TCK and has an internal pull-up
resistor. This input is 5 V tolerant.
Test Data Output
A test data serial signal for test instructions and data. TDO can be
tri-stated. The signal is actively driven in the shift-IR and shift-DR
controller states and changes on the falling edge of TCK. This pin is
5 V tolerant.
Test Mode Select
Sequences the test controller’s state machine, is sampled on the
rising edge of TCK, and has an internal pull-up resistor. This input is
5 V tolerant.
Test Reset
Asynchronously initializes the test controller, has an internal pull-up
resistor, and must be asserted after power up. This input is 5 V
tolerant.
Timer 1 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO1 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO1 is
output. The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output through
the Timer 1 Control/Status Register (TCSR1). This input is 5 V
tolerant.
Timer 2 Schmitt-Trigger Input/Output
As an external event counter or in Measurement mode, TIO2 is
input. In Watchdog, Timer, or Pulse Modulation mode, TIO2 is
output. The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output through
the Timer 2 Control/Status Register (TCSR2). This input is 5 V
tolerant.
Signal Description
Signal Description
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