SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 191

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

configured as input. A hardware
bits.
8.7.3 Port E Data Register (PDRE)
Bits 2–0 of the read/write 24-bit PDRE writes data to or reads data from the associated SCI signal
lines when configured as GPIO signals. If a port signal PE[i] is configured as an input (GPI), the
corresponding PDRE[i] bit reflects the value present on the input signal line. If a port signal PE[i]
is configured as an output (GPO), a value written to the corresponding PDRE[i] bit is reflected as
a value on the output signal line. Either a hardware
instruction clears all PDR bits.
Freescale Semiconductor
Note:
Note:
23
11
23
11
For bits 2–0, a 0 configures PEn as a GPI and a 1 configures PEn as a GPO. For the SCI, the GPIO signals are
PE[2–0]. The corresponding direction bits for Port E GPIOs are PRRE[2–0].
For bits 2–0, the value represents the level that is written to or read from the associated signal line if enabled as a
GPIO signal by the PCRE bits. For SCI, the GPIO signals are PE[2–0]. The corresponding data bits are PDRE[2–0].
= Reserved. Read as zero. Write with zero for future compatibility.
= Reserved. Read as zero. Write with zero for future compatibility.
22
10
22
10
Figure 8-9. Port E Direction Register (PRRE X:$FFFF9E)
21
21
9
9
Figure 8-10. Port Data Registers (PDRE X:$FFFF9D)
20
20
8
8
RESET
DSP56303 User’s Manual, Rev. 2
19
19
7
7
signal or a software RESET instruction clears all PRRE
18
18
6
6
RESET
17
17
5
5
signal or a software RESET
16
16
4
4
15
15
3
3
PRRE2
PDRE2
GPIO Signals and Registers
14
14
2
2
PDRE1
PRRE1
13
13
1
1
PRRE0
PDRE0
12
12
0
0
8-23