SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 148

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
7-16
Sync:
Async:
Sync:
Async:
These signals are
identical in sync mode.
TX Word
TX 1, or
Flag0
RX clk
TX/RX clk
TX clk
Clock
Word
RX
F
SCn0
CORE
SCKn
Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
CRA(DC4–0)
CRA(DC4:0)
CRB(SCD0)
CRB(SCKD)
Figure 7-3. ESSI Clock Generator Functional Block Diagram
/1 to /32
CRB(FSL[1–0])
Transmit
/1 to /32
Receive
Control
Control
0
0
Logic
Logic
/2
CRB(FSR)
31
31
CRB(TE1)
TX 1
(Sync Mode)
Frame Sync
Transmit
Frame Sync
Receive
or
CRA(PSR)
(Opposite
from SSI)
SYN = 0
CRB(SYN) = 0
/1 or /8
Flag0 Out
CRB(OF0)
1
CRB(SYN) = 1
Sync-
Type
Sync
Type
DSP56303 User’s Manual, Rev. 2
0
SYN =
CRB(FSL1)
CRB(FSR)
(Sync Mode)
Internal Rx Frame Sync
SSISR(IF0)
SCD0 = 1
Internal Bit Clock
CRA(PM7:0)
Flag0 In
/1 to /256
CRB(SCD1) = 1
0
Internal TX Frame Sync
SCD1 =
SCD0 = 0
255
(Sync Mode)
SSISR(IF1)
Flag1 In
SYN = 0
SYN = 1
RCLOCK
TCLOCK
• F
• ESSI internal clock range:
• ‘n’ in signal name is ESSI # (0 or 1)
clock frequency.
min = F
max = F
CORE
SYN = 1
SYN = 0
CRB(TE2)
TX 2,
RX Shift Register
is the DSP56300 core internal
OSC
OSC
TX Shift Register
0
0
/8, /12, /16, /24,
CRA(WL2–0)
CRA(WL2–0)
/8, /12, /16, /24,
/4096
/4
1
1
Flag1 Out,
CRB(OF1)
(Sync Mode)
CRB(SCD1)
2
2
CRB(SCD2)
3 4,5
3 4,5
Freescale Semiconductor
or drive enb.
CRA(SSC1)
Sync:
Async:
TX 2 Flag1,
or drive enb.
RX F.S.
SCn1
SCn2
Sync:
Async:
TX/RX F.S.
TX F.S.
RX
Word
Clock
TX
Word
Clock