SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 268

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming Reference
B-24
Receive Exception Interrupt Enable
Application:
ESSI
0 = Disable
Transmit Exception Interrupt Enable
ESSI Control Register B (CRBx)
Reset = $000000
0 = Disable
23 22 21 20
REIE
Receive Last Slot Interrupt Enable
0 = Disable
Transmit Last Slot Interrupt Enable
0 = Disable
Receive Interrupt Enable
TEIE
0 = Disable
Transmit Interrupt Enable
0 = Disable
Receiver Enable
RLIE
0 = Disable
Transmit 0 Enable
0 = Disable
Transmit 1 Enable (SYN=1 only)
1 = Enable
0 = Disable
Transmit 2 Enable (SYN=1 only)
TLIE
1 = Enable
0 = Disable
Mode Select
1 = Enable
0 = Normal
Sync/Async Control
(Tx & Rx transfer together or not)
1 = Enable
19 18 17 16
RIE
1 = Synchronous
0 = Asynchronous
1 = Enable
1 = Enable
Figure B-15. ESSI Control Register B (CRB)
TIE
1 = Enable
1 = Enable
1 = Enable
RE
1 = Enable
1 = Network
TE0
DSP56303 User’s Manual, Rev. 2
15 14 13 12 11 10 9
TE1 TE2 MOD SYN CKP
ESSI0—X:$FFFFB6 Read/Write
ESSI1—X:$FFFFA6 Read/Write
Clock Polarity
(clk edge data & Frame Sync clocked out/in)
0 = out on rising/in on falling
1 = in on rising/out on falling
Frame Sync Polarity
FSP FSR FSL1
1 = low level (negative)
0 = high level (positive)
Frame Sync Relative Timing
(WL Frame Sync only)
1 = 1 clock cycle earlier than first data bit
0 = with first data bit
FSL1
0
0
1
1
Shift Direction
8
Clock Source Direction
0 = MSB First
0 = External Clock
FSL0
FSL0
7
0
1
0
1
SC0
SC1
SC2
Pin
Serial Control Direction Bits (see Table 7-2)
SHFD
Word
Bit
Bit
Word
6
Date:
Programmer:
Frame Sync
TX
Length
SCKD SCD2 SCD1 SCD0 OF1 OF0
Rx Clk
Rx Frame Sync
Tx Frame Sync
5
SCDx = 0 (Input)
Word
Word
Bit
Bit
1 = LSB First
RX
Output Flag x
4
If SYN = 1 and SCD1 = 1
OFx → SCx Pin
1 = Internal Clock
3
Freescale Semiconductor
2
Sheet 2 of 3
Flag 0
Flag 1
Tx, Rx Frame Sync
SCDx = 1 (Output)
1
0