C500CP131 Omron, C500CP131 Datasheet - Page 231

• Manufacturer Part Number: C500CP131
• Description: C-SERIES SPECIAL I/O UNIT
• Manufacturer: Omron

Specifications of C500CP131

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PC Setup
226
Letter
G
H
J
I
Execution
controls 2
(Execute
control 2)
Host link
CPU bus link setting
Scheduled interrupt interval
Execute process
I/O interrupts
Power OFF
interrupt
Duplicate action
error
Step timer
Startup trace
Indirect DM
binary/BCD
(*DM BIN/BCD)
Multiple use of
JMP000
Comparison error
process
Baud rate
Stop bits
Parity
Data length
(Data bits)
Unit number
Name
Designate whether instruction execution and Peripheral Device servicing are
to be carried out synchronously or asynchronously. If synchronous execution
is used, IOM cannot be accessed from a Peripheral Device during user
program execution.
(Default: Parallel)
Designate whether or not I/O interrupt execution is interrupted for
higher-priority I/O interrupts. The I/O interrupt program with the lowest input
number has highest priority.
Power OFF interrupts, power ON interrupts, and scheduled interrupts take
priority over I/O interrupts regardless of this setting.
This setting is effective immediately.
(Default: Nesting)
Designate whether or not power OFF interrupts are generated. If an interrupt
is generated, the power OFF interrupt program will be executed. This setting
is effective immediately.
(Default: Disable)
Designate whether or not a non-fatal SFC error is generated when the same
action is executed simultaneously from multiple program steps. This setting
is effective immediately.
(Default: Error)
Designate whether the step timer is set in increments of 0.1 s or 1.0 s. This
setting is effective immediately.
(Default: 0.1 s)
Designate whether a trace is executed automatically according to the preset
conditions when the power is turned on or the operating mode is changed.
This setting is effective the next time power is turned on.
(Default: Don’t start trace)
Designate whether indirect DM and EM addresses are binary (PC memory
addresses) or BCD (DM and EM area addresses). This setting is effective
immediately.
(Default: BCD)
To specify where or not multiple JMP000 instructions can be programmed.
(Default: Multiple use of JMP000 enabled)
Designate whether or not to enable operation for I/O verification errors. Once
the PC starts operating, the operation continues even if an I/O verification
error has occurred. This setting is effective immediately.
(Default: Run after error)
Designate 1200, 2400, 4800, 9600, or 19200 bps.
(Default: 9600 bps)
Designate either 1 stop bit or 2 stop bits.
(Default: 2 stop bits)
Designate even, odd, or no parity.
(Default: Even parity)
Designate either 7-bit or 8-bit data.
(Default: 7-bit data)
Designate the unit number between 00 and 31. The unit number must not be
the same as the unit number of another PC. This setting is effective
immediately.
(Default: 00)
Designate whether or not CPU bus links are used. CPU bus links are used
between BASIC Units only. The CPU bus link service interval is 10 ms. Any
change in setting will be reflected immediately.
(Default: Don’t use CPU bus link)
Designate whether the scheduled interrupt time is set in increments of 10.0
ms, 1.0 ms, or 0.5 ms. This setting is effective the next time the power is
turned ON.
(Default: 10 ms)
Operation
Section 7-2