C500CP131 Omron, C500CP131 Datasheet - Page 228

• Manufacturer Part Number: C500CP131
• Description: C-SERIES SPECIAL I/O UNIT
• Manufacturer: Omron

Specifications of C500CP131

• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PC Setup
Letter
M
D
E
G
H
K
F
L
J
I
Startup processing
I/O refresh
Execution
controls 1
(Execute
control 1)
Execution
controls 2
(Execute
control 2)
Host link
CPU bus link setting
Scheduled interrupt
First words for local racks
(1st Rack addr)
First words for group-1 and
group-2 Slaves (SYSMAC BUS/2)
(Group 1,2 1st addr)
First words for I/O Terminals
(Trans I/O addr)
Detect low battery
Error on power off
CPU standby
Measure CPU Bus
Unit (CPU SIOU) cycle
Execute process
I/O interrupts
Power OFF interrupt
Duplicate action error
Step timer
Startup trace
Indirect DM
binary/BCD
(*DM BIN/BCD)
Multiple use of
JMP000
Comparison error
process
Name
To specify whether the user
program is loaded from the
Memory Card when power is
turned on.
To set the refresh method to cyclic,
zero-cross, or scheduled.
To specify detection of CPU battery
errors.
To specify if momentary power
interruptions are to be treated as
errors.
To specify whether the CPU is to go on standby or start operation while
initializing the system or detecting terminators in SYSMAC BUS/2
Systems.
To specify whether or not the CPU Bus Unit servicing cycle is to be
measured.
To specify whether Peripheral
Devices are to be serviced
synchronously or asynchronously
with program execution.
To specify whether higher-priority I/O interrupts are to be executed before
a current I/O interrupt.
To specify whether a power off
interrupt is to be executed.
To specify whether an error is to be generated when the same action is
executed simultaneously from two different locations in the program.
To set the unit for the step timer to 0.1 or to 1 s.
To specify whether a trace is to be automatically executed when power is
turned on.
To specify whether indirect
addresses are treated as binary
(memory addresses) or BCD (data
area addresses).
To specify where or not multiple JMP000 instructions can be
programmed.
To specify whether I/O verification errors are to be fatal or non-fatal.
To set communications parameters
for the host link interface.
To specify whether or not CPU bus
links are to be created.
To set the unit for setting the scheduled interrupt to 10.0, 1.0, or 0.5 ms.
To set the first word for each of the
CPU, Expansion CPU, and
Expansion I/O Racks.
To set the first word for group-1 and
group-2 Slaves for each Master.
To set the first word for I/O
Terminals for each Master.
Function
To enable using a ROM Memory
Card without a backup battery.
To reduce the cycle time by using
immediate refreshing or to reduce
surge voltages for AC outputs.
To disable detection when batteries
are not being used.
To generate an error for momentary
power interrupts when they
adversely affect system operation.
To increase processing capacity
(speed) by using asynchronous
processing.
To save system status when power
turns off.
To enable indirectly addresses for
the entire DM and EM areas by
using binary addresses.
These settings must be made when
using the host link interface.
To enable linking of two or more
BASIC Units.
To simplify word allocations, to
prevent changes in allocations, or
to allow for expansion without
changes in allocations.
To prevent overlapping of word
allocations when group-1 and
group-2 Slaves require more then
50 words per Master.
To separate I/O Terminal
allocations from those for other
Slaves.
Normal application(s)
Section 7-2
223