HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 895
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.1
The user break controller (UBC) provides functions that simplify program debugging. When break
conditions are set in the UBC, a user break interrupt is generated according to the contents of the
bus cycle generated by the CPU. This function makes it easy to design an effective self-monitoring
debugger, enabling programs to be debugged with the chip alone, without using an in-circuit
emulator.
20.1.1
The UBC has the following features.
• Two break channels (A and B)
• The following can be set as break compare conditions:
• An instruction access cycle break can be effected before or after the instruction is executed.
User break interrupts can be generated on independent conditions for channels A and B, or on
sequential conditions (sequential break setting: channel A → channel B).
⎯ Address (selection of 32-bit virtual address and ASID for comparison):
⎯ Data (channel B only, 32-bit mask capability)
⎯ Bus cycle: Instruction access/operand access
⎯ Read/write
⎯ Operand size: Byte/word/longword/quadword
Address: All bits compared/lower 10 bits masked/lower 12 bits masked/lower 16 bits
masked/lower 20 bits masked/all bits masked
ASID: All bits compared/all bits masked
Overview
Features
Section 20 User Break Controller (UBC)
Rev.4.00 Oct. 10, 2008 Page 795 of 1122
20. User Break Controller (UBC)
REJ09B0370-0400
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