HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 847
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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18.1
This LSI has a 32-bit general-purpose I/O port, SCI I/O port, and SCIF I/O port.
18.1.1
The features of the general-purpose I/O port are as follows:
• Available only in PCI-disabled mode.
• 32-bit I/O port with input/output direction independently specifiable for each bit.
• Pull-up can be specified independently for each bit.
• The 32 bits of the general-purpose I/O port are divided into 16-bit port A and 16-bit port B.
• Use or non-use of the I/O port can be selected with the PORTEN bit in bus control register 2
The features of the SCI I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCI enabling has not been
• The RxD pin value can be read at all times, allowing break state detection.
• SCK pin control is possible when the I/O port is designated for output and SCI enabling has
• The SCK pin value can be read at all times.
The features of the SCIF I/O port are as follows:
• Data can be output when the I/O port is designated for output and SCIF enabling has not been
• The RxD2 pin value can be read at all times, allowing break state detection.
• SCK2, CTS2, and RTS2 pin control is possible when the I/O port is designated for output and
• The SCK2, CTS2, and RTS2 pin values can be read at all times.
Interrupts can be input to 16-bit port A.
(BCR2). (Do not set PORTEN = 1 when in PCI-enabled mode.)
set. This allows break function transmission.
not been set.
set. This allows break function transmission.
SCIF enabling has not been set.
Overview
Features
Section 18 I/O Ports
Rev.4.00 Oct. 10, 2008 Page 747 of 1122
REJ09B0370-0400
18. I/O Ports
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