HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 375

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.4
10.4.1
The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies
use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU
clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be
used on FRQCR.
FRQCR is initialized only by a power-on reset via the RESET pin. The initial value of each bit is
determined by the clock operating mode.
Bits 15 to 12—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 11—Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO
pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the high-
impedance state, operation continues at the operating frequency before this state was entered.
When the CKIO pin becomes high-impedance, it is pulled up.
Bit 11: CKOEN
0
1
Note:
Initial value:
Initial value:
*
R/W:
R/W:
CPG Register Description
Frequency Control Register (FRQCR)
Bit:
Bit:
It is not pulled up in hardware standby mode.
IFC1
R/W
R/W
15
0
7
Description
CKIO pin goes to high-impedance state (pulled up*)
Clock is output from CKIO pin
IFC0
R/W
R/W
14
0
6
BFC2
R/W
R/W
13
0
5
BFC1
R/W
12
R
0
4
Rev.4.00 Oct. 10, 2008 Page 275 of 1122
CKOEN PLL1EN PLL2EN
BFC0
R/W
R/W
11
1
3
10. Clock Oscillation Circuits
PFC2
R/W
R/W
10
1
2
REJ09B0370-0400
PFC1
R/W
R/W
9
1
1
(Initial value)
PFC0
IFC2
R/W
R/W
8
0

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