HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 88

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 23.12 (1) Pin Drive Timing for Standby Mode ........................................................... 1008
Figure 23.12 (2) Pin Drive Timing for Software Standby Mode............................................ 1009
Figure 23.13 SRAM Bus Cycle: Basic Bus Cycle (No Wait) ................................................. 1014
Figure 23.14 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) .................................. 1015
Figure 23.15 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)
Figure 23.16 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/
Figure 23.17 Burst ROM Bus Cycle (No Wait) ...................................................................... 1018
Figure 23.18 Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
Figure 23.19 Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
Figure 23.20 Burst ROM Bus Cycle (One Internal Wait + One External Wait) ..................... 1021
Figure 23.21 Synchronous DRAM Auto-Precharge Read Bus Cycle: Single
Figure 23.22 Synchronous DRAM Auto-Precharge Read Bus Cycle: Burst
Figure 23.23 Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Figure 23.25 Synchronous DRAM Normal Read Bus Cycle: READ Command, Burst
Figure 23.26 Synchronous DRAM Auto-Precharge Write Bus Cycle: Single
Figure 23.27 Synchronous DRAM Auto-Precharge Write Bus Cycle: Burst
Figure 23.28 Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Figure 23.29 Synchronous DRAM Normal Write Bus Cycle: PRE + ACT +
Figure 23.30 Synchronous DRAM Normal Write Bus Cycle: WRITE Command,
Figure 23.31 Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) ....... 1032
Figure 23.32 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001)
Figure 23.33 Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001) .................... 1034
Figure 23.34 (a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL)............... 1035
Figure 23.34 (b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET) ................. 1036
Rev.4.00 Oct. 10, 2008 Page lxxxvi of xcviii
REJ09B0370-0400
Hold Time Insertion, AnS = 1, AnH = 1)........................................................... 1017
2nd/3rd/4th Data: One Internal Wait)................................................................. 1019
AnS = 1, AnH = 1) ............................................................................................. 1020
(RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ...................................... 1022
(RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ...................................... 1023
Burst (RASD = 1, RCD [1:0] = 01, CAS Latency = 3)...................................... 1024
Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001,
CAS Latency = 3)............................................................................................... 1025
(RASD = 1, CAS Latency = 3) .......................................................................... 1026
(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010).................................... 1027
(RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010).................................... 1028
Burst (RASD = 1, RCD [1:0] = 01, TRWL [2:0] = 010) ................................... 1029
WRITE Commands, Burst (RASD = 1, RCD [1:0] = 01, TPC [2:0] = 001,
TRWL [2:0] = 010) ............................................................................................ 1030
Burst (RASD = 1, TRWL [2:0] = 010) .............................................................. 1031
1016
1033