HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 38

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xxxvi of xcviii
REJ09B0370-0400
Item
19.1.3 Pin
Configuration
Table 19.1 INTC Pins
19.2.1 NMI Interrupt
19.2.2 IRL Interrupts
19.2.3 On-Chip
Peripheral Module
Interrupts
19.2.4 Interrupt
Exception Handling and
Priority
Table 19.4 Interrupt
Exception Handling
Sources and Priority
Order
19.4.1 Interrupt
Operation Sequence
Page
771
772
774
775
777
787
Description amended
Description amended
Revision (See Manual for Details)
Table amended
NMI interrupt exception handling does not affect the interrupt
mask level bits (IMASK) in the status register (SR).
The interrupt mask bits (IMASK) in the status register (SR) are
not affected by IRL interrupt handling.
Description amended
The interrupt mask bits (IMASK) in the status register (SR) are
not affected by on-chip peripheral module interrupt handling.
Table amended
Interrupt Source
PCIC
Description amended
3. The priority level of the interrupt selected by the interrupt
Notes: 1. The interrupt mask bits (IMASK) in the status
Pin Name
Nonmaskable interrupt
input pin
Interrupt input pins
controller is compared with the interrupt mask bits (IMASK)
in the status register (SR) of the CPU. If the request priority
level is higher that the level in bits IMASK, the interrupt
controller accepts the interrupt and sends an interrupt
request signal to the CPU.
PCISERR
PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
register (SR) are not changed by acceptance of an
interrupt in this LSI.
INTEVT
Code
H'A00
H'AE0
H'AC0
H'AA0
H'A80
H'A60
H'A40
H'A20
Function
Input of nonmaskable interrupt request
signal
Input of interrupt request signals
(maskable by IMASK in SR)
Interrupt Priority
(Initial Value)
15–0 (0)
15–0 (0)
IPR (Bit
Numbers)
INTPRI00
(3–0)
INTPRI00
(7–4)
Priority within
IPR Setting Unit
—
High
Low
Default
Priority
High