HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 229
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.6.4
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed are specified in the address field, and
the longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is
specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry
specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to
cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary
of Memory-Mapped OC Addresses. Address field bits [4:2] are used for the longword data
specification in the entry. As only longword access is used, 0 should be specified for address field
bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the OC data array:
Legend:
V:
U:
A:
Address field
occurs during address translation, or the comparison shows a mismatch, an exception is not
generated, no operation is performed, and the write is not executed. If a data TLB multiple hit
exception occurs during address translation, processing switches to the data TLB multiple hit
exception handling routine.
: Reserved bits (0 write value, undefined read value)
Data field
Validity bit
Dirty bit
Association bit
OC Data Array
31
31
1 1 1 1 0 1 0 0
Figure 4.14 Memory-Mapped OC Address Array
24
23
Tag
15
Rev.4.00 Oct. 10, 2008 Page 129 of 1122
Way
14
13
10 9
Entry
REJ09B0370-0400
5 4 3 2 1 0
4. Caches
A
2
U
1 0
V
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