HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 349

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you
9.4.2
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip
peripheral module) or a reset.
9.5
9.5.1
Changing the SLEEP pin to the low level causes this LSI to make a transition to sleep mode.
To ensure that memory is correctly refreshed, use this function when the DSLP bit of STBCR2 is
set to 0.
9.5.2
Setting the SLEEP pin level high causes this LSI to return to the normal state. The pin sleep mode
is also canceled when the conditions specified in section 9.3.2, “Exit From Sleep Mode” are
satisfied.
In a power-on reset, the SLEEP pin should be fixed high.
9.6
9.6.1
If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches
from the program execution state to standby mode. In standby mode, the on-chip peripheral
modules halt as well as the CPU. Clock output from the CKIO pin is also stopped.
The CPU and cache register contents are retained. Some on-chip peripheral module registers are
initialized. The state of the peripheral module registers in standby mode is shown in table 9.4.
Exit from Deep Sleep Mode
Pin Sleep Mode
Transition to Pin Sleep Mode
Exit from Pin Sleep Mode
Standby Mode
Transition to Standby Mode
make a transition to deep sleep mode while DMA transfers are in progress, the results
of those transfers cannot be guaranteed.
Rev.4.00 Oct. 10, 2008 Page 249 of 1122
9. Power-Down Modes
REJ09B0370-0400