HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 887

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.4
19.4.1
The sequence of operations when an interrupt is generated is described below. Figure 19.3 shows a
flowchart of the operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
3. The priority level of the interrupt selected by the interrupt controller is compared with the
4. The CPU accepts an interrupt at a break between instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
The interrupt handler may branch with the INTEVT register value as its offset in order to identify
the interrupt source. This enables it to branch to the handling routine for the particular interrupt
source.
Notes: 1. The interrupt mask bits (IMASK) in the status register (SR) are not changed by
according to the priority levels set in interrupt priority registers A to D (IPRA–IPRD) and
interrupt priority register 00 (INTPRI00). Lower-priority interrupts are held pending. If two of
these interrupts have the same priority level, or if multiple interrupts occur within a single
module, the interrupt with the highest priority according to table 19.4, Interrupt Exception
Handling Sources and Priority Order, is selected.
interrupt mask bits (IMASK) in the status register (SR) of the CPU. If the request priority level
is higher that the level in bits IMASK, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
vector base register (VBR) and H'00000600).
2. The interrupt source flag should be cleared in the exception handling routine. To ensure
3. Depending on the interrupt factor, the interrupt mask (INTMSK00) must be cleared for
INTC Operation
Interrupt Operation Sequence
acceptance of an interrupt in this LSI.
that an interrupt request that should have been cleared is not inadvertently accepted
again, read the interrupt source flag after it has been cleared, then wait for the interval
shown in table 19.8 (Time for priority decision and SR mask bit comparison) before
clearing the BL bit or executing an RTE instruction.
each factor using the INTMSKCLR00 register. See section 19.3.5, Interrupt Mask
Register 00 (INTMSK00), and section 19.3.6, Interrupt Mask Clear Register 00
(INTMSKCLR00), for details.
Rev.4.00 Oct. 10, 2008 Page 787 of 1122
19. Interrupt Controller (INTC)
REJ09B0370-0400