HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 555

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
BS
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)
In a cycle of access to synchronous DRAM, the BS signal is asserted for one clock cycle at the
beginning of a bus cycle. Data are accessed in the following sequence: in the fill operation for
a cache miss, the data between the 32-bit boundaries that include the missed data are first read;
after that, the data between 32-byte boundaries that include the missed data are read in a
wraparound way.
Tr
Row
Row
Row
Trw
Tc1
c1
H/L
Tc2
Tc3
Tc4/Td1
c1
Td2
c2
Td3
Rev.4.00 Oct. 10, 2008 Page 455 of 1122
c3
Td4
c4
Td5
13. Bus State Controller (BSC)
c5
Td6
c6
Td7
REJ09B0370-0400
c7
Td8
c8
Tpc

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