HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 32

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xxx of xcviii
REJ09B0370-0400
Item
13.3.15 Notes on
Usage
Page
495, 496 Description amended
Revision (See Manual for Details)
Refresh: Auto refresh operations stop when a transition is made
to standby mode, hardware standby mode, or deep-sleep
mode. If the memory system requires refresh operations, set
the memory in the self-refresh state prior to making the
transition to standby mode, hardware standby mode, or deep-
sleep mode.
…
Synchronous DRAM Mode Register Settings (SH7751 Only):
The following conditions must be satisfied when setting the
synchronous DRAM mode register.
•
•
Notes: 1. If a conflict occurs between synchronous DRAM
The DMAC must not be activated until synchronous DRAM
mode register setting is completed.*
Register setting for the on-chip peripheral modules*
not be performed until synchronous DRAM mode register
setting is completed.*
2. This applies to the following on-chip peripheral
3. If synchronous DRAM mode register setting is
mode register setting and memory access using the
DMAC, neither operation can be guaranteed.
modules: CPG, RTC, INTC, TMU, SCI, SCIF, and
H-UDI.
performed immediately following write access to the
on-chip peripheral modules*
the on-chip peripheral modules cannot be
guaranteed. Note that following power-on,
synchronous DRAM mode register settings should
be performed before accessing synchronous
DRAM. After making mode register settings, do not
change them.
3
1
2
, the values written to
2
must