HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 982
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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22. PCI Controller (PCIC)
When B'11 is written to bits 1 and 0 and a transition is made to power state D3 (power down
mode), PCIC operation as a master target is disabled, regardless of the setting of bits 2 to 0 of the
PCICONF1 (bus master control, memory and I/O space access control) (these bits are masked).
When B'00 is written to bits 1 and 0 and a transition is made to power state D0 (normal operating
mode), the mask is canceled.
Bits 31 to 24—DATA (DATA7 to 0): Not supported. Data field for power management.
Bits 23 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 15—PME Status (PMEST): Not supported. Shows the status of the PME bit. This bit is set
when the signal is output.
Bits 14 and 13—Data Scale (DTATSCL1 to 0): Not supported. These bits specify the scaling
value for the data field value.
Bits 12 to 9—Data Select (DATASEL3 to 0): Not supported. Select the value to be output to the
data field.
Bit 8—PME Enable (PMEEN): Not supported. Controls the PME signal output.
Bits 7 to 2—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bits 1 and 0—Power State (PWRST1 and 0): Specifies the power state. No state transition is
effected when a non-supported state is specified. (Normal termination, no error output.)
Bit 1: PWRST1
0
1
Rev.4.00 Oct. 10, 2008 Page 882 of 1122
REJ09B0370-0400
Bit 0: PWRST0
0
1
0
1
Description
D0 state (Initial value, normal state)
D1 state (not supported)
D2 state (not supported)
D3 state (power down mode)
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