HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 785

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 5—Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from
SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit
trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and
new transmit data can be written to SCFTDR2.
Bit 5: TDFE
0
1
Note:
Bit 4—Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 4: BRK
0
1
Note:
*
*
As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be
written when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of
this will be ignored.
The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2.
When a break is detected, the receive data (H'00) following detection is not transferred
to SCFRDR2. When the break ends and the receive signal returns to mark “1”, receive
data transfer is resumed.
Description
A number of transmit data bytes exceeding the transmit trigger set number
have been written to SCFTDR2
[Clearing conditions]
•
•
The number of transmit data bytes in SCFTDR2 does not exceed the
transmit trigger set number
[Setting conditions]
•
•
Description
A break signal has not been received
[Clearing conditions]
•
•
A break signal has been received*
[Setting condition]
When data with a framing error is received, followed by the space “0” level
(low level ) for at least one frame length
When transmit data exceeding the transmit trigger set number is written
to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE
When transmit data exceeding the transmit trigger set number is written
to SCFTDR2 by the DMAC
Power-on reset or manual reset
When the number of SCFTDR2 transmit data bytes falls to or below the
transmit trigger set number as the result of a transmit operation*
Power-on reset or manual reset
When 0 is written to BRK after reading BRK = 1
16. Serial Communication Interface with FIFO (SCIF)
Rev.4.00 Oct. 10, 2008 Page 685 of 1122
REJ09B0370-0400
(Initial value)
(Initial value)