HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 289

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7.1
PC: PC indicates the address of the instruction itself.
Data sizes and data types: The SH-4 instruction set is implemented with 16-bit fixed-length
instructions. The SH-4 can use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-
bit) data sizes for memory access. Single-precision floating-point data (32 bits) can be moved to
and from memory using longword or quadword size. Double-precision floating-point data (64 bits)
can be moved to and from memory using longword size. When a double-precision floating-point
operation is specified (FPSCR.PR = 1), the result of an operation using quadword access will be
undefined. When the SH-4 moves byte-size or word-size data from memory to a register, the data
is sign-extended.
Load-Store Architecture: The SH-4 features a load-store architecture in which operations are
basically executed using registers. Except for bit-manipulation operations such as logical AND
that are executed directly in memory, operands in an operation that requires memory access are
loaded into registers and the operation is executed between the registers.
Delayed Branches: Except for the two branch instructions BF and BT, the SH-4 branch
instructions and RTE are delayed branches. In a delayed branch, the instruction following the
branch is executed before the branch destination instruction. This execution slot following a
delayed branch is called a delay slot. For example, the BRA execution sequence is as follows:
Static Sequence
BRA
ADD
next_2
Delay Slot: A slot illegal instruction exception may occur when a specific instruction is executed
in a delay slot. See section 5, Exceptions. The instruction following BF/S or BT/S for which the
branch is not taken is also a delay slot instruction.
TARGET
R1, R0
Execution Environment
Section 7 Instruction Set
Dynamic Sequence
BRA
ADD
target_instr
TARGET
R1, R0
Rev.4.00 Oct. 10, 2008 Page 189 of 1122
ADD in delay slot is executed before
branching to TARGET
REJ09B0370-0400
7. Instruction Set