HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 24

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Rev.4.00 Oct. 10, 2008 Page xxii of xcviii
REJ09B0370-0400
Item
13.2.8 Memory Control
Register (MCR)
13.2.8 Memory Control
Register (MCR)
13.2.10 Synchronous
DRAM Mode Register
(SDMR)
Page
377
378
379
380
387
Revision (See Manual for Details)
Description amended of Bit 31
Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS
down mode is used, set BE to 1. Do not set RAS down mode in
slave mode
synchronous DRAM interface.
Table amended of Bit 31
Bit 31: RASD
0
1
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
Note added, Bits 29 to 27
Note: For setting values and the period during which no
Description and note added, Bits 21 to 19
Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the
DRAM interface is selected, these bits specify the minimum
number of cycles until RAS is asserted again after being
negated. When the synchronous DRAM interface is selected,
these bits specify the minimum number of cycles until the next
bank active command after precharging.
Note: For setting values and the period during which no
Description amended of Bits 15 to 13
After a write cycle, the next active command is not issued for a
period set by TPC[2:0] and TRWL[2:0] bits*. …
Note:
Description amended of Bits 12 to 10
Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period
(TRAS2–TRAS0): When the DRAM interface is set, these bits
set the RAS assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active
command is not issued for a period set by TPC[2:0] and
TRAS[2:0] bits after an auto-refresh command is issued.
Note: For setting values and the period during which no
Description amended
LMODE: CAS latency
BL:
WT:
and bits A3IW2–A3IW0 to 000.
command is issued, see 23.3.3, Bus Timing.
command is issued, see 23.3.3, Bus Timing.
command is issued, see 23.3.3, Bus Timing.
*
Burst length
Wrap type (0: Sequential)
For setting values and the period during which no
command is issued, see 23.3.3, Bus Timing.
Description
Auto-pre
RAS down mode
areas 2 and 3 are both designated as
charge mode
(Initial value)