HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 337

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Exceptions:
4. Conditional branch latency “2 (or 1)”: The latency is 2 for a nonzero displacement, and
5. Double-precision floating-point instruction latency “(L1, L2)/L3”: L1 is the latency for FR
6. FTRV latency “(L1, L2, L3, L4)/L5”: L1 is the latency for FR [n], L2 that for FR [n+1], L3
7. Latency “L1/L2/L3/L4” of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2
8. Latency “L1/L2” of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions:
9. Execution pattern: The instruction execution pattern number (see figure 8.2)
10. Lock/stage: Stage locked by the instruction
11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.
12. Lock/cycles: Number of cycles locked
1. When a floating-point computation instruction is followed by an FMOV store, an STS
2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the
3. When an LS group instruction with a latency of less than 3 cycles is followed by a
4. When MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is followed by an
5. In the case of consecutive executions of
6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn
7. When an LDS to MACH/MACL is followed by
8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that
9. When a single-precision FTRC instruction is followed by an STS FPUL, Rn instruction,
1 for a zero displacement.
[n+1], L2 that for FR [n], and L3 that for FPSCR.
that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
that for Rn, L3 that for MACH, and L4 that for MACL.
L1 is the latency for MACH, and L2 that for MACL.
FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floating-
point computation is decreased by 1 cycle.
latency of the load is increased by 1 cycle.
double-precision floating-point instruction, FIPR, or FTRV, the latency of the first
instruction is increased to 3 cycles.
Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2
STS.L MACH/MACL, @-Rn instruction, the latency of
MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is 5 cycles.
MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L, the latency is
decreased to 2 cycles.
instruction, the latency of the LDS to MACH/MACL is 4 cycles.
MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L, the latency of the LDS
to MACH/MACL is 1 cycle.
reads or writes to a floating-point register, the preceding LS group instruction[s] cannot
be executed in parallel.
the latency of the single-precision FTRC instruction is 1 cycle.
cycles.
Rev.4.00 Oct. 10, 2008 Page 237 of 1122
REJ09B0370-0400
8. Pipelining