HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 41

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
22.2.3 PCI
Configuration Register 2
(PCICONF2)
22.2.17 PCI Control
Register (PCICR)
22.2.24 PCI Arbiter
Interrupt Register
(PCIAINT)
Page
864
886
887
900
901
Revision (See Manual for Details)
Description amended
Bits 23 to 16—Sub Class Codes (CLASS15 to 8): Shows the
subclass code. For details, please see appendix D, Pin
Functions of the PCI Local Bus Specifications, Revision 2.1.
Bits 15 to 8—Register Level Programming Interface (CLASS7
to 0): Shows the register level programming interface. For
details, please see appendix D, Pin Functions of the PCI Local
Bus Specifications, Revision 2.1.
Description added of Bit 3
Description deleted of Bit 1
Description amended
The PCIAINT register is initialized to H'00000000 at a power-on
reset or software reset.
Description added of Bit 13
Bit 13—Master Broken Interrupt (MST_BRKN): Detects when
the master granted with bus privileges does not start a
transaction (FRAME not asserted) within 16 clocks. For the
SH7751, see 22.12, Usage Notes.
Description added of Bit 12
Bit 12—Target Bus Timeout Interrupt (TGT_BUSTO): Neither
TRDY nor STOP are not returned within 16 clocks in the case
of the first data transfer, or within 8 clocks in the case of second
and subsequent data transfers. For the SH7751, see 22.12,
Usage Notes.
Description added of Bit 11
Bit 11—Master Bus Timeout Interrupt (MST_BUSTO): Indicates
the detection that IRDY was not asserted within 8 clock cycles
in a transaction initiated by a device including PCIC.
Description amended of Bit 1
Bit 1—Write Data Parity Error Interrupt (DPERR_WT): Indicates
the detection of the assertion of PERR in a data write operation
when a device other than the PCIC is operating as the bus
master.
Bit 3: SERR
0
1
Description
SERR pin at Hi-Z (driven to High by pull-up resistor)
A
ssert SERR (Low output)
Rev.4.00 Oct. 10, 2008 Page xxxix of xcviii
REJ09B0370-0400
(Initial value)