HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 653

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5
14.5.1
Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT
mode). In DDT mode, it is possible to transfer to channel 0 to 3 via the data bus and DDT module,
and simultaneously issue a transfer request, using the DBREQ, BAVL, TR, TDACK, ID [1:0],
DTR.ID, and DTR.MD signals between an external device and the DMAC. Figure 14.23 shows a
block diagram of the DMAC, DDT, BSC, and an external device (with DBREQ, BAVL, TR,
TDACK, ID [1:0], DTR.ID, and DTR.MD pins).
After first making the normal DMA transfer settings for DMAC channels 0 to 3 using the CPU, a
transfer request is output from an external device using the DBREQ, BAVL, TR, TDACK,
DTR.ID [1:0], and DTR.MD [1:0] signals (handshake protocol using the data bus). A transfer
request can also be issued simply by asserting TR, without using the external bus (handshake
protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the
normal way, a transfer request can be issued directly from an external device (with DBREQ,
BAVL, TR, TDACK, DTR.ID [1:0], and DTR.MD [1:0] pins) by asserting DBREQ and TR
simultaneously .
In DDT mode, there is a choice of five modes for performing DMA transfer.
ddtmode tdack id[1:0]
DMAC
BSC
On-Demand Data Transfer Mode (DDT Mode)
Operation
DMATCR0
DREQ0–3
CHCR0
SAR0
DAR0
Data buffer
Figure 14.23 On-Demand Transfer Mode Block Diagram
ddtmode
bavl
BAVL
DBREQ
TDACK
ID[1:0]
DDT
controller
Request
buffer
Data
TR
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 553 of 1122
DTR
REJ09B0370-0400
DBREQ, BAVL,
TR, TDACK,
device (with
and ID [1:0])
memory
FIFO or
External
Memory