HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1069

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.6
22.6.1
There are 8 interrupts, as shown in the following, that can be generated by the PCIC for the CPU.
The interrupt controller also controls the individual interrupt priority levels and interrupt masks,
etc. See the section 19, Interrupt Controller (INTC), for details.
Table 22.13 Interrupts
Interrupt Source
PCISERR
PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
System Error (SERR) Interrupt (PCISERR): This interrupt shows detection of the SERR pin
being asserted. This interrupt is generated only when the PCIC is operating as host.
When the PCIC is operating as non-host, the SERR bit in the PCI control register (PCICR) is used
to notify the host device of the system error (assertion of SERR pin).
The SERR pin can be asserted when the SERR bit is asserted and when an address parity error is
detected in a target transfer.
When the SER bit of the PCI configuration register 1 (PCICONF1) is set to 0, the SERR pin is not
asserted.
Error Interrupt (PCIERR): Shows error detection by the PCIC. The error interrupt is asserted
when either of the following errors is detected:
• Interrupts detected by PCI interrupt register (PCIINT)
• Interrupts detected by PCI arbiter interrupt register (PCIAINT)
Interrupts
Interrupts from PCIC to CPU
Function
SERR error interrupt
ERR error interrupt
Power-down request interrupt
Power-on request interrupt
DMA0 transfer end interrupt
DMA1 transfer end interrupt
DMA2 transfer end interrupt
DMA3 transfer end interrupt
Rev.4.00 Oct. 10, 2008 Page 969 of 1122
INTPRI00
[3:0]
[7:4]
22. PCI Controller (PCIC)
Priority
High
Low
REJ09B0370-0400
High
Low