HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 33
HD6417751RF240V
Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417751RBP200DV.pdf
(1226 pages)
Specifications of HD6417751RF240V
Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Item
14.1.1 Features
14.2.4 DMA Channel
Control Registers 0-3
(CHCR0-CHCR3)
14.3.4 Types of DMA
Transfer
(a) Normal DMA Mode
Table 14.8 External
Request Transfer
Sources and
Destinations in Normal
DMA Mode
(b) DDT Mode
Table 14.9 External
Request Transfer
Sources and
Destinations in DDT
Mode
Page
498, 499 Description amended
508
533
534
Revision (See Manual for Details)
⎯ On-chip peripheral modules request
…
Note:
Description added
Bit 28—Source Address Wait Control Select (STC): Specifies
CS5 or CS6 space wait control for PCMCIA interface area
access. This bit selects the wait control register in the BSC that
performs area 5 and 6 wait cycle control.
Table title amended
Table amended
1
2
3
4
5
6
Transfer Source
Synchronous DRAM
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA
*
Transfer Direction (Settable Memory Interface)
DTR.COUNT [7:4] (DTR [23:20]): Sets the port as
not used. In DDT mode on the SH7751, an external
device and the DMAC perform handshaking using
the DBREQ, BAVL, TR, TDACK, ID[1:0], and
D[31:0] signals during data transfer. On the
SH7751R, the DBREQ, BAVL, TR, TDACK, ID[2:0],
and D[31:0] signals are used for handshaking
during data transfer between an external device and
the DMAC.
Rev.4.00 Oct. 10, 2008 Page xxxi of xcviii
*
*
Transfer Destination
External device with DACK
Synchronous DRAM
SRAM-type, MPX, PCMCIA
Synchronous DRAM
SRAM-type, MPX, PCMCIA
SRAM-type, DRAM, PCMCIA,
MPX
REJ09B0370-0400
*
*
Address
Mode
Single
Single
Dual
Dual
Dual
Dual
Usable
DMAC
Channels
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
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