HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 655

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.5.2
Figure 14.24 shows the system configuration in DDT mode.
• DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR
• BAVL: Data bus D31–D0 release signal
• TR: Transfer request signal
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL.
Assertion of BAVL means that the data bus will be released two cycles later.
Assertion of TR has the following different meanings.
⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same
⎯ In the case of the handshake protocol without use of the data bus, asserting TR enables a
⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
A25–A0, RAS, CAS, WE, DQMn, CKE
time the DTR format is output, two cycles after BAVL is asserted.
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when BAVL is not asserted two cycles
earlier.
can be made to channel 2 by asserting DBREQ and TR simultaneously.
Pins in DDT Mode
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
SH7751/SH7751R
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D31–D0 = DTR
Synchronous
DRAM
14. Direct Memory Access Controller (DMAC)
Rev.4.00 Oct. 10, 2008 Page 555 of 1122
External device
REJ09B0370-0400