HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1063

MPU 1.5/3.3V 0K PB-FREE 256-QFP

HD6417751RF240V

Manufacturer Part Number
HD6417751RF240V
Description
MPU 1.5/3.3V 0K PB-FREE 256-QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417751RF240V

Core Processor
SH-4
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-QFP Exposed Pad, 256-eQFP, 256-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417751RF240V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.4.4
In target transfers, for memory read and memory write that perform data transfer between the local
bus and the PCI bus, big/little endian conversion is required in the same way as for DMA transfers
when the local bus is set for big endians. Word/longword boundary modes are not supported in the
case of target transfers. As shown in table 22.12, the byte data boundary mode is used, for all
transfers.
The access sizes supported in the case of target transfers are as follows: For target reads (local bus
to PCI bus), longword only. For target writes (PCI bus to local bus), longword/word/byte. In target
write operations, the byte, word and longword data in the PCIC are transferred to the local bus in
one or two transfer operations depending on the type of the byte enable signal of the PCI bus.
For example, when C/BE = B'1010, byte access to the local bus is generated twice. When C/BE =
B'1000, byte access and word access are each generated once.
Table 22.12 Target Transfer Access Size and Endian Conversion Mode
Local Bus
Endian
Big endian
Little endian
Endian Control in Target Transfers (Memory Read/Memory Write)
Data Transfer
Direction
Target read
Target write
Target read
Target write
Access
Size
LW
B, W, LW
LW
B, W, LW
W/LW Boundary
Mode (1 to 3)
No
No
Conversion not
required
Rev.4.00 Oct. 10, 2008 Page 963 of 1122
Endian Conversion Mode
22. PCI Controller (PCIC)
Byte Data Boundary
Mode
Yes
Conversion not
required
Yes
REJ09B0370-0400

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