HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 533

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Burst Write: The timing chart for a burst write is shown in figure 13.26. In this LSI, a burst write
occurs only in the event of 32-byte transfer. In a burst write operation, the WRIT command is
issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output and, 4
cycles later, the WRITA command is issued. In the write cycle, the write data is output at the same
time as the write command. In the case of the write with auto-precharge command, precharging of
the relevant bank is performed in the synchronous DRAM after completion of the write command,
and therefore no command can be issued for the same bank until precharging is completed.
Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is
also added as a wait interval until precharging is started following the write command. Issuance of
a new command for the synchronous DRAM is postponed during this interval. The number of
Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR. Access starts from 16-byte
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(read)
BS
CKE
DACKn
(SA: IO ← memory)
Figure 13.25 Basic Timing for Synchronous DRAM Single Read
Tr
Row
Row
Row
Trw
Tc1
Tc2
Tc3 Tc4/Td1 Td2
Rev.4.00 Oct. 10, 2008 Page 433 of 1122
H/L
c1
c1
13. Bus State Controller (BSC)
Td3
Td4
Tpc
REJ09B0370-0400